Cell structure of non-volatile memory device and method for fabricating the same

ABSTRACT

A cell structure of a non-volatile memory device, which uses a nitride layer as a floating gate spacer, includes a gate stack and a floating gate transistor formed over a semiconductor substrate. The gate stack includes a first portion of a floating gate, a control gate formed over the first portion of the floating gate, and a non-nitride spacer adjacent to sidewalls of the first portion of floating gate. The floating gate transistor includes a second portion of the floating gate, which substantially overlaps a source and/or drain formed in the substrate. The application of ultraviolet rays to the non-nitride spacer of a programmed cell can causes the second portion of the floating gate to discharge, thereby easily erasing the programmed cell.

[0001] This application claims the priority of Korean Patent ApplicationNo. 2003-01815 filed on Jan. 11, 2003, in the Korean IntellectualProperty Office, the contents of which are incorporated herein byreference in its entirety.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor memory device,and more particularly, to the cell structure of anon-volatile memorydevice.

[0004] 2. Description of the Related Art

[0005] Semiconductor memory devices can be classified into random accessmemories (RAMs) and read only memories (ROMs). When an interruption inpower supply occurs, data stored in a RAM is erased, while a ROMmaintains its stored data. For this reason, ROMs are classified as“nonvolatile memory devices.” An erasable programmable read-only memory(EPROM) device is a particular type of nonvolatile memory devices, whichis reusable by allowing its stored data to be erased. One variation ofEPROM devices is a flash memory device, which allows data to be erasedin blocks (two or more bytes) rather than one byte at a time.

[0006] Data stored in the EPROM device can be erased by applyingultraviolet rays to a window attached to the surface of a memory chip.Research is being conducted to develop system-on-chip (SOC) devices,which include EPROM devices along with various devices, such as logiccircuits or drive circuits. The EPROM devices can be used while the SOCdevices are being manufactured, for example, to calibrate disparitybetween devices or represent manufacturers' names on fabricated chips.

[0007] As the line widths of circuits have become finer, the fabricationprocesses of semiconductors increasingly use silicide layers, such asTiSix, CoSix, and NiSix, to reduce the resistances of gate lines andmetal contacts. When a silicide layer is used, a nitride layer isapplied as a gate spacer for the transistor, rather than an oxide layer.This improves the characteristics of the transistor by preventing ashort between the gate and either the source or drain during thesilicidation process.

[0008] When a cell of the EPROM device is formed by a process using anitride layer as the gate spacer, an ONO (oxide-nitride-oxide) layer isformed on top of a floating gate, and a nitride spacer is formed on thesides of the floating gate. That is, the process forms nitride layersall around the floating gate. In such a case, it becomes difficult toerase charges of the floating gate by ultraviolet rays, sinceultraviolet layers cannot pass through the nitride layers.

SUMMARY OF THE INVENTION

[0009] Exemplary embodiments of the present invention provide a cellstructure for a non-volatile device using a nitride layer as a floatinggate spacer, which allows charges of the floating gate to be erased byapplying ultraviolet rays to an exposed non-nitride spacer.

[0010] Exemplary embodiments of the present invention also provide amethod for fabricating the cell structure of the non-volatile memorydevice.

[0011] According to an exemplary embodiment, the cell structure of anon-volatile memory device comprises a gate stack, which includes afirst portion of a floating gate formed over a semiconductor substrate,a control gate formed over the first portion of the floating gate, and anon-nitride spacer adjacent to sidewalls of the first portion of thefloating gate. In an exemplary embodiment, the cell structure of thenon-volatile memory device further comprises a floating gate transistor,which includes a second portion of the floating gate formed over thesemiconductor substrate so that is substantially overlaps a portion of asource and/or drain implanted in the substrate.

[0012] According to an exemplary embodiment, the non-nitride spacer maybe a double layer formed of a polysilicon spacer and an oxide spacer.

[0013] According to exemplary embodiments, the gate stack may includethe nitride layer in an insulating pattern between the control gate andthe first portion of the floating gate, and the floating gate transistormay include a nitride spacer adjacent to sidewalls of the second portionof the floating gate. A nitride spacer may also be adjacent to sidewallsof the control gate.

[0014] According to an exemplary embodiment, when a first voltage isapplied to the control gate of the gate stack and a second voltage isapplied to the second portion of the floating gate of the floating gatetransistor, charges may be injected to the first portion of the floatinggate from the source and/or the drain by hot carrier injection, therebyprogramming the cell. In a further exemplary embodiment, the charges canbe discharged from the first portion of the floating gate to the sourceand/or drain by applying ultraviolet rays to the exposed non-nitridespacer of the gate stack, thereby erasing the programmed cell.

[0015] According to an exemplary embodiment of the present invention,the cell structure may be implemented in an EPROM device or a flashmemory.

[0016] In accordance with an exemplary embodiment of the presentinvention, a method for fabricating a cell structure of a non-volatilememory device includes forming a floating gate over a semiconductorsubstrate, such that a first portion of the floating gate is formed overa gate stack region of the substrate and a second portion of thefloating gate and a second portion of the floating gate is formed over afloating gate transistor region of the substrate; forming a control gateover at least a part of the first portion of the floating gate of thegate stack region; and forming a non-nitride spacer adjacent tosidewalls of the first portion of the floating gate.

[0017] According to an exemplary embodiment, impurity ions may beimplanted into the semiconductor substrate so as to implant a sourceand/or a drain at least partially in the floating gate transistorregion, such that the floating gate substantially overlaps a portion ofthe implanted source and/or drain.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Various features and advantages of the present invention willbecome readily apparent in view of the detailed description of exemplaryembodiments set forth below with reference to the attached drawings, inwhich like reference numerals designate like structural elements, and,in which:

[0019]FIG. 1 illustrates a cell layout of a non-volatile memory deviceaccording to an exemplary embodiment of the present invention;

[0020]FIGS. 2A and 2B illustrate cross-sectional views taken along theline A-A′ of a gate stack and the line B-B′ of a floating gatetransistor of FIG. 1, respectively, according to exemplary embodimentsof the present invention;

[0021]FIGS. 3A, 4A, 5A, 6A, 7A, 8A, and 9A illustrate variouscross-sectional views of the gate stack during a fabrication process ofa cell of the non-volatile memory device according to exemplaryembodiments of the present invention; and

[0022]FIGS. 3B, 4B, 5B, 6B, 7B, 8B, and 9B illustrate variouscross-sectional views of the floating gate transistor during afabrication process of a cell of the non-volatile memory deviceaccording to exemplary embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0023] The present invention and exemplary embodiments thereof are morefully described below with reference to the accompanying drawings. Thisinvention may, however, be embodied in many different forms and shouldnot be construed as being limited to the exemplary embodiments set forthherein. Rather, these exemplary embodiments are provided so that thisdisclosure is thorough and complete, and conveys the concept of theinvention to those skilled in the art. In the drawings, the thicknessesof layers and regions are exaggerated for clarity. Further, it will beunderstood that when a layer is referred to as being “on” or “formedover” another layer or substrate, the layer may be directly on the otherlayer or substrate, or intervening layers may also be present.

[0024]FIG. 1 illustrates a cell layout of a non-volatile memory deviceaccording to an exemplary embodiment of the present invention.

[0025] Specifically, the cell of the non-volatile memory deviceaccording to an exemplary embodiment of the present invention includes afloating gate 106 formed over a semiconductor substrate (not shown). Thefloating gate 106 can be contemplated as comprising two portions, wherea first portion 106 a of the floating gate 106 is included in a gatestack 200 and a second portion 106 b is included in a floating gatetransistor 400 of the cell structure.

[0026] In an exemplary embodiment, the cell structure of thenon-volatile memory device includes a gate stack 200 on a semiconductorsubstrate (not shown). The gate stack 200 may include the first portionof the floating gate 106 a, an insulating pattern (not shown) formedover the first portion of the floating gate 106 a, a control gate 131formed over the insulating pattern, and a non-nitride spacer 122surrounding the first portion of floating gate 106 a.

[0027] The floating gate 106 (including the first portion 106 a, as wellas the second portion 106 b) may be formed of a polysilicon doped withimpurity ions. In an exemplary embodiment, the insulating pattern isformed at least partially of a nitride layer. For example, theinsulating pattern may be formed of an oxide-nitride-oxide (ONO) layeror a nitride-oxide (NO) layer. The control gate 131 can be a doublelayer formed of a polysilicon doped with impurity ions and a suicidelayer. According to an exemplary embodiment, the non-nitride spacer 122can be a double layer formed of a polysilicon spacer and an oxidespacer.

[0028] According to an exemplary embodiment illustrated in FIG. 1, thecell of the non-volatile memory device further includes a floating gatetransistor 400, in which a gate insulating layer (not shown) is formedover the semiconductor substrate, a second portion of the floating gate106 b is formed over the gate insulating layer, and a source and drain(collectively referred to as 127). The source and drain is implanted inthe semiconductor substrate so as to be aligned with the second portionof the floating gate 106 b. As shown in FIG. 1, a nitride spacer 124 asurrounds the second floating gate 106 b according to an exemplaryembodiment.

[0029] In an exemplary embodiment, the source and drain 127 are alignedwith the second portion of the floating gate 106 b so that at least onesidewall of the second portion 106 b perpendicularly overlaps a narrowportion of the source and drain 127. Like the first portion 106 a, thesecond portion of the floating gate 106 b may be formed of a polysilicondoped with impurity ions.

[0030] According to an exemplary embodiment of the present invention,the cell structure illustrated in FIG. 1 is operable as follows. When aparticular voltage (i.e., first voltage level) is applied to the controlgate 131 of the gate stack 200, and another voltage (i.e., secondvoltage level) is applied to the second portion of the floating gate 106b, charges are injected from the source and/or drain 127 into the firstportion of the floating gate 106 a by hot carrier injection. Thus, thecell is programmed. The voltages may be applied via metal contactscoupled to the control gate 131 and the second portion of the floatinggate 106 b.

[0031] The specific voltage levels to be applied to both the controlgate 131 and the second portion of the floating gate 106 b will bereadily apparent and obvious to those of ordinary skill in the art.

[0032] According to another exemplary embodiment, however, a voltage maybe applied directly to one, or both, of the source and drain 127 (e.g.,via a metal contact) rather than the second portion of the floating gate106 b in order to program the cell. For instance, hot carrier injectioncan occur when a first voltage level is applied to the control gate 131and a second voltage level is applied to the drain 127, while the sourceis grounded. According to an exemplary embodiment, the first voltagelevel applied to control gate 131 can be substantially within the rangeof 11-13 volts and the second voltage level applied to the drain 127 canbe substantially within the range of 5-7 volts (while no voltage isapplied to the source 127 or substrate. However, the present inventionis not limited to such an embodiment, and covers any combination ofapplied voltage levels used for programming the cell, as will be readilyapparent to those of ordinary skill in the art.

[0033] In an exemplary embodiment, ultraviolet rays can be applied to atleast a portion of exposed surface area, or the entire exposed surfacearea, of the non-nitride spacer 122 in the gate stack 200 of aprogrammed cell, in order to discharge the charges from the firstportion of the floating gate 106 a to the source and/or drain 127. Thus,the programmed cell is erased.

[0034] In an exemplary embodiment, the cell structure explained aboveand illustrated in FIG. 1 may be implemented in an EPROM device, a flashmemory device, or any other non-volatile memory device that uses anitride layer as a spacer of a floating gate, as will be readilycontemplated by those ordinarily skilled in the art.

[0035] Although FIG. 1 second portion of the floating gate 106 b asbeing narrower than the first portion 106 a, this is merely illustrativeof one exemplary embodiment and does not limit the present invention.

[0036] For example, the surface areas of the first and second portion106 a and 106 b may have the same width, and the source and drain 127may be disposed further apart from one another, so that the secondportion of the floating gate 106 b overlaps only a narrow portion of thesource and/or drain 127. Other obvious modifications of theconfiguration shown in FIG. 1, as will be contemplated by those ofordinary skill in the art, are covered by exemplary embodiments of thepresent invention.

[0037]FIGS. 2A and 2B illustrate cross-sectional views taken along theline A-A′ of the gate stack 200 and the line B-B′ of the floating gatetransistor 400 of FIG. 1, respectively, according to an exemplaryembodiment of the present invention.

[0038] Referring to FIG. 2A, the gate stack 200 includes a fieldinsulating layer 102 formed over the semiconductor substrate 101. In thegate stack, the first portion of the floating gate 106 a, the insulatingpattern 114, and the control gate 131 are sequentially formed over thefield insulating layer 102. As described above, the first portion of thefloating gate 106 a can be formed of a polysilicon doped with impurityions. The insulating pattern 114 can be formed of three differentlayers, including an oxide (O) layer 108, a nitride (N) layer 110, andanother oxide (O) layer 112. In an alternative exemplary embodiment, theinsulating pattern 114 may be formed of only two layers—a nitride layer110 and an oxide layer 112.

[0039] As shown in FIG. 2A, the surface area of the first portion of thefloating gate 106 a can cover the same area as that of the insulatingpattern 114. The control gate 131 can be formed of a polysilicon 118doped with impurity ions and a silicide layer 129. According to anexemplary embodiment, the surface area of the control gate 131 does notcover the entire area of the first portion of the floating gate 106 a. Anitride spacer 124 a is formed adjacent to both sidewalls of the controlgate 131. However, a non-nitride spacer 122 is formed adjacent to bothsidewalls of the first portion of the floating gate 106 a instead of anitride spacer. The non-nitride spacer 122 may include both apolysilicon spacer 120 and an oxide spacer 121, as shown in FIG. 2A.

[0040] In exemplary embodiments of the present invention, all of, or atleast a portion of, the surface area of the non-nitride spacer 122 isexposed. Thus, according to an exemplary embodiment, by applyingultraviolet rays over the entire gate stack 200, at least some of theultraviolet rays will be applied to exposed portions of the non-nitridespacer 122, thus allowing charges to be discharged from the firstportion of the floating gate 106 a in a programmed cell.

[0041] Unlike a conventional cell structure of a non-volatile memoryusing a nitride spacer, the cell structure of the non-volatile memorydevice shown in FIG. 2A includes a non-nitride spacer 122 (e.g., thepolysilicon spacer 120 and oxide spacer 121) adjacent to both sidewallsof the first floating gate 106 a. Thus, ultraviolet rays can be appliedthrough the non-nitride spacer 122 (e.g., through the oxide layer 121)to the cell structure of the non-volatile memory device and easily erasethe programmed cell.

[0042] Referring to FIG. 2B, the floating gate transistor 400 maycomprise a gate insulating pattern 104 a, the second portion of thefloating gate 106 b, and an insulating pattern 114 a formed of a nitridelayer, all of which cover the same surface area on the semiconductorsubstrate 101. Similar to the insulating layer 114 of the gate stack 200described above, the insulating pattern 114 a may be formed of an oxidelayer 108, a nitride layer 110, and an oxide layer 112. Alternatively,the insulating pattern 114 a may be formed of only the nitride layer 110and the oxide layer 112.

[0043] The source and drain 127 may be implanted in the semiconductorsubstrate 101 so as to be aligned with the sidewalls of the secondportion of the floating gate 106 b. Based on this alignment, at leastone sidewall of the second portion of the floating gate 106 b mayperpendicularly overlap, by a narrow margin, either the source or drain127. In a further exemplary embodiment, both sidewalls of the secondportion of the floating gate 106 b may perpendicularly overlap with acorresponding one of the source and drain 127.

[0044] According to exemplary embodiments, the source and/or drain 127may be positioned in the semiconductor substrate 101 so as to beactually, or substantially, overlapped by the second portion of thefloating gate 106 b.

[0045] According to an exemplary embodiment, each of the source anddrain 127 may include a lightly doped region 123 and a heavily dopedregion 125.

[0046] As shown in the exemplary embodiment of FIG. 2B, a nitride spacer124 b is formed adjacent to both sidewalls of the second floating gate106 b. However, in exemplary embodiments where the second portion of thefloating gate 106 b only overlaps one of the source and drain 127, thenitride spacer 124 b may only be adjacent to the particular sidewalloverlapping the source/drain 127.

[0047] Thus, unlike the conventional cell structure, the non-volatilememory device cell structure according to exemplary embodiments, asshown in FIG. 2B, the nitride spacer 124 b can prevent a short betweenthe second portion of the floating gate 106 b and the source and/ordrain 127 during a silicidation process for forming the silicide layer129 over the source and drain 127. Thus, the characteristics of thefloating gate transistor 400 can be improved.

[0048]FIGS. 3A, 4A, 5A, 6A, 7A, 8A, and 9A illustrate variouscross-sectional views illustrating the gate stack 200 during afabrication process of a cell of a non-volatile memory device, accordingto exemplary embodiments of the present invention. FIGS. 3B, 4B, 5B, 6B,7B, 8B, and 9B illustrate cross-sectional views of the floating gatetransistor 400 during a fabrication process of a cell of a non-volatilememory device according to exemplary embodiments of the presentinvention.

[0049] Referring to FIGS. 3A and 3B, a region of the gate stack 200 anda region of the floating gate transistor 400 can be defined on asemiconductor substrate 101, for example, a silicon substrate. A fieldinsulating layer 102 can be formed over the semiconductor substrate 101.A region of the cell over which the field insulating layer 102 is formedcan be referred to as an “isolation region,” while a region of the cellover which the field insulating layer 102 is not formed can be referredto as an “active region.”

[0050] As shown in FIG. 3B, a gate insulating layer 104 can be formedover the floating gate transistor region of the semiconductor substrate101. According to an exemplary embodiment, the gate insulating layer 104can be formed of an oxide layer with a thickness of 100 to 200 Å.

[0051] As shown in FIGS. 3A and 3B, a polysilicon layer doped withimpurity ions can be formed over the field insulating layer 102 of thegate stack region and the gate insulating layer 104 of the floating gatetransistor region so as to form the floating gate 106. The firstpolysilicon layer of the floating gate 106 is formed to a thickness of1000 to 1500 Å.

[0052] Referring to FIGS. 4A and 4B, the polysilicon layer forming thefloating gate 106 can be patterned, or etched, to be narrowed to aparticular width across the gate stack and floating gate transistorregions. According to an exemplary embodiment, this step patterns thepolysilicon layer to an appropriate width for the first portion of thefloating gate 106 a of the gate stack region (as shown in FIG. 4A).

[0053] On the other hand, this width may not be an appropriate finalwidth for the second portion of the floating gate 106 b. Thus, as shownin FIG. 4B, the portion of the etched polysilicon layer can be referredto as an intermediary polysilicon pattern 106′ on the floating gatetransistor region. According to an exemplary embodiment, theintermediary polysilicon pattern 106′ can be etched down to anappropriate width to form the second portion floating gate 106 b insubsequent patterning steps of the fabrication process (as illustratedin FIG. 7B).

[0054] During the step where the polysilicon layer is etched into thefirst portion of the floating gate 106 a and the intermediarypolysilicon pattern 106′, the respective field insulating layer 102 andgate insulating layer 104 may also be etched. As a result, the firstportion of the floating gate 106 a and the intermediary polysiliconpattern 106′ may cover the same surface area of the semiconductorsubstrate 101 as that covered by the field insulating layer 102 and gateinsulating layer 104, respectively.

[0055] Referring to FIGS. 5A and 5B, an insulating pattern 114 can beformed over the first portion of the floating gate 106 a and thepolysilicon pattern 106′. This insulating pattern 114 can be formed ofan oxide layer 108, a nitride layer 110, and another oxide layer 112.According to an exemplary embodiment, the oxide layer 108, nitride layer110, and oxide layer 112 can be formed substantially to thicknesses of100 Å, 200 Å, and 100 Å, over the surface areas of the first portion ofthe floating gate 106 a and the intermediary polysilicon pattern 106′.

[0056] In an alternative embodiment, the step corresponding to FIGS. 5Aand 5B forming the insulating pattern 114 to include only a nitridelayer 110 and an oxide layer 112.

[0057] Further referring to FIGS. 5A and 5B, another polysilicon layer116 doped with impurity ions may be formed over the entire gate stackregion the entire surfaces of the gate stack and floating gatetransistor regions of semiconductor substrate 101, after the insulatingpattern 114 is formed.

[0058] Referring to FIGS. 6A and 6B, the polysilicon layer 116 ispatterned, or etched, to form a polysilicon pattern 118 over theinsulating pattern 114 of the gate stack region. The polysilicon pattern118 on the insulating pattern 114 a layer of the control gate to beformed over the gate stack region.

[0059] Also, as shown in FIGS. 6A and 6B, the polysilicon layer 116 canbe patterned to form a polysilicon spacer 120 adjacent to both sidewallsof the first portion of the floating gate 106 a and the intermediarypolysilicon pattern 106′ of the floating gate transistor region. Thus,the formed polysilicon spacer 120 that is adjacent to the sidewalls ofthe first portion of the floating gate 106 a on the gate stack regioncan be made part of a non-nitride spacer 122 for the gate stack of thecell.

[0060] According to an exemplary embodiment, the polysilicon layer 116may be etched such that there is no polysilicon pattern 118 formed onthe first insulating pattern 114 of the floating gate transistor, asshown in FIG. 6B.

[0061] Referring to FIG. 7B, the insulating pattern 114, theintermediary polysilicon pattern 106′, and the gate insulating layer 104may be patterned, e.g., using photolithographic and etching processes,to form the insulating pattern 114 a, second portion of the floatinggate 106 b, and gate insulating pattern 104 a, respectively, of afloating gate transistor 400. Also, as shown in FIG. 7B, the polysiliconspacer 120 formed on the both sidewalls of the first polysilicon pattern106′ of the floating gate transistor can be removed.

[0062] As shown in FIG. 7A, an oxide spacer 121 may be formed over thepolysilicon spacer 120 of the gate stack region to thereby form anon-nitride spacer 122. According to an exemplary embodiment, the oxidespacer 121 can be obtained by oxidizing the polysilicon spacer 120.

[0063] In addition, an oxidation process of the second portion of thefloating gate 106 b can also be carried out in order to prevent etchingdamage during the etching process that forms the second floating gate106 b, and to improve characteristics of the floating gate transistor400 by thickening the oxide layer disposed under the sides of thetransistor 400.

[0064] Referring to FIGS. 8A and 8B, impurity ions can be implanted intothe semiconductor substrate 101 to be aligned with the sidewalls of thesecond portion of the floating gate 106 b, thereby forming thelightly-doped regions 123 corresponding to a source and drain, as shownin FIG. 8B. As described above, the implantation of these lightly dopedregions 123 should be such that a small portion of the source and/or thedrain is overlapped by a sidewall of the second portion of the floatinggate.

[0065] Also, as shown in FIGS. 8A and 8B, a nitride layer 124 may beformed over the entire surface of the gate stack and floating transistorregions of the semiconductor substrate 101.

[0066] Referring to FIGS. 9A and 9B, the nitride layer 124 can be etchedusing an anisotropic etching process so as to form the nitride spacer124 a adjacent to both sidewalls of the polysilicon pattern 118 of thegate stack region. Also, the nitride layer 124 can be etched to form thenitride spacer 124 b adjacent to both the sidewalls of the secondportion of the floating gate 106 b of the floating gate transistorregion.

[0067] As illustrated in FIG. 9B, impurity ions can be implanted intothe semiconductor substrate 101 so as to be aligned with the formednitride spacer 124 b, thereby forming the heavily doped regions 125 of asource and drain. As a result, the source and the drain 127, each ofwhich includes a lightly doped region 123 and a heavily doped region125, is formed in the semiconductor substrate 101.

[0068] As shown in FIGS. 2A and 2B, a silicide layer 129 can be formedover the polysilicon pattern 118 and the source/drain 127 in anexemplary embodiment. The silicide layer can help reduce the resistanceto any voltages subsequently applied to these areas via a metal contact.According to this exemplary embodiment, a control gate 131 is formed,which includes not only the polysilicon pattern 118, but also thesilicide layer 129.

[0069] By forming a non-nitride spacer 122, rather than a nitridespacer, adjacent to the sidewalls of the first portion of the floatinggate 106 a, exemplary embodiments of the present invention allow aprogrammed cell in a non-volatile memory device to be easily erased byapplying ultraviolet rays to the non-nitride spacer 122.

[0070] Furthermore, by forming the nitride spacer 124 b adjacent to thesidewalls of a second portion of the floating gate 106 b, exemplaryembodiments help prevent shorts from occurring between the secondportion of the floating gate 106 b and a source/drain 127.

[0071] While the present invention has been particularly shown anddescribed with reference to the exemplary embodiments described above,it will be understood by those of ordinary skill in the art that variouschanges in form and details may be made therein without departing fromthe spirit and scope of the present invention as defined by thefollowing claims.

What is claimed is:
 1. A cell structure of non-volatile memory deviceusing a nitride layer as a floating gate spacer comprising: a gate stackincluding, a first portion of a floating gate formed over asemiconductor substrate, a control gate formed over at least part of thefirst portion of the floating gate, and an exposed non-nitride spaceradjacent to sidewalls of the first portion of the floating gate; and afloating gate transistor including, a second portion of the floatinggate formed over the semiconductor substrate to substantially overlap aportion of at least one of a source and drain implanted in thesemiconductor substrate.
 2. The cell structure of claim 1, wherein thegate stack further includes, an insulating pattern including a nitridelayer between the control gate and the first portion of the floatinggate.
 3. The cell structure of claim 1, wherein the floating gatetransistor further includes, a nitride spacer adjacent to sidewalls ofthe second portion of the floating gate
 4. The cell structure of claim1, wherein the non-nitride spacer includes a polysilicon layer and anoxide layer.
 5. The cell structure of claim 1, further comprising: anitride spacer adjacent to sidewalls of the control gate.
 6. The cellstructure of claim 1, wherein the first and second portions of thefloating gate comprise a polysilicon doped with impurity ions.
 7. Thecell structure of claim 1, further comprising: an insulating pattern ofthe gate stack formed between the second portion of the floating gateand the semiconductor substrate, the insulating pattern including atleast one of an oxide-nitride-oxide (ONO) layer and a nitride-oxide (NO)layer.
 8. The structure of claim 1, wherein the control gate includes apolysilicon layer doped with impurity ions and a silicide layer, and asilicide layer is formed on the source and drain.
 9. The cell structureof claim 1, wherein the non-volatile memory device is at least one of anerasable programmable read-only memory device (EPROM) and a flash memorydevice.
 10. The cell structure of claim 1, wherein the at least one ofan implanted source and drain is operable to inject charges into thefirst portion of the floating gate in response to a first voltage beingapplied to the control gate and a second voltage being applied to thesecond portion of the floating gate, thereby programming a correspondingcell of the non-volatile memory device.
 11. The cell structure of claim8, wherein the first portion of the floating gate is operable todischarge the injected charges to the at least one of an implantedsource and drain in response to ultraviolet rays being applied to theexposed non-nitride spacer of the gate stack, thereby erasing theprogrammed cell.
 12. A method for fabricating a cell structure of anon-volatile memory device, the method comprising: forming a floatinggate over a semiconductor substrate, a first portion of the floatinggate being formed over a gate stack region of the semiconductorsubstrate, and a second portion of the floating gate being formed over afloating gate transistor region of the semiconductor substrate; forminga control gate over at least a part of the first portion of the floatinggate; and forming a non-nitride spacer adjacent to sidewalls of thefirst portion of the floating gate.
 13. The method of claim 12, furthercomprising: implanting impurity ions into the semiconductor substrate toimplant a source and drain at least partially in the floating gatetransistor region of the semiconductor substrate, wherein the secondportion of the floating gate substantially overlaps a portion of atleast one of the implanted source and drain.
 14. The method of claim 13,further comprising: forming a nitride spacer over the floating gatetransistor region, the formed nitride spacer being adjacent to sidewallsof the second portion of the floating gate; and forming a silicide layerover the control gate, and over portions of the source and drain overwhich neither the second portion of the floating gate, nor the nitridespacer, is formed.
 15. The method of claim 12, wherein the step offorming the non-nitride spacer includes, forming a polysilicon spacerover the gate stack region, the formed polysilicon spacer being adjacentto sidewalls of the first portion of the floating gate, and forming anoxide spacer over the formed polysilicon spacer.
 16. The method of claim12, wherein a nitride spacer is formed over the first portion of thefloating gate, the formed nitride spacer being adjacent to sidewalls ofthe control gate.
 17. The method of claim 12, wherein the step offorming the floating gate includes forming a polysilicon doped withimpurity ions over the gate stack and floating gate transistor regions.18. The method of claim 12, further comprising: forming an insulatingpattern over the gate stack region, the insulating pattern including atleast one of an oxide-nitride-oxide (ONO) layer and a nitride-oxide (NO)layer.
 19. The method of claim 12, wherein the step of forming thecontrol gate includes forming a polysilicon doped with impurity ions anda suicide layer over the first portion of the floating gate.
 20. Themethod of claim 12, wherein the step of forming the floating gateincludes, forming a field insulating pattern over the gate stack region;forming a gate insulating pattern over the floating gate transistorregion; forming a polysilicon pattern over the gate stack region and thefloating gate transistor region, the first portion of the floating gatecomprising a part of the polysilicon pattern formed over the gate stackregion, the second portion of the floating gate comprising a part of thepolysilicon pattern formed over the floating gate transistor region. 21.The method of claim 20, further comprising: etching at least the firstportion of the floating gate to expose a surface area of the fieldinsulating layer.
 22. The method of claim 21, further comprising:forming an insulating pattern including a nitride layer over the firstand second portions of the floating gate.
 23. The method of claim 21,further comprising: forming a polysilicon layer doped with impurity ionsover the first portion of the floating gate and the exposed surface areaof the field insulating layer; and etching the formed polysilicon layerto form the control gate over the first portion of the floating gate.24. The method of claim 23, wherein: the step of etching the formedpolysilicon layer forms a polysilicon spacer over the exposed surfacearea of the field insulating layer, the polysilicon spacer beingadjacent to sidewalls of the first portion of the floating gate, and thestep of forming the non-nitride spacer includes oxidizing thepolysilicon spacer.
 25. A non-volatile memory whose cell structure ismanufactured according to the method of claim
 12. 26. A non-volatilememory including: a floating gate formed over a semiconductor substrate;a non-nitride spacer adjacent to a first portion of the floating gate;and a nitride spacer adjacent to a second portion of the floating gate,the second portion substantially overlapping at least one of a sourceand drain in the semiconductor substrate.
 27. The non-volatile memory ofclaim 26, further comprising: a control gate formed over the firstportion of the floating gate.
 28. The non-volatile memory of claim 27,wherein the at least one of the source and drain is operable to injectcharges into the floating gate via hot carrier injection, therebyprogramming a cell in the non-volatile memory.
 29. The non-volatilememory of claim 28, wherein the control gate is operable to receive afirst voltage; at least one of the source, drain, and second portion ofthe floating gate is operable to receive a second voltage; and thereceiving of the first and second voltages causes the at least one ofthe source and drain to inject the charges via hot carrier injection.30. The non-volatile memory, wherein the first portion of the floatinggate is operable to discharge charges in response to ultraviolet raysbeing applied to at least a portion of the non-nitride spacer, therebyerasing a programmed cell in the non-volatile memory.